Semiconductor devices with replacement gate structures

ABSTRACT

A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.

BACKGROUND

1. Field of the Disclosure

The present disclosure is generally directed to the fabrication ofintegrated circuits, and, more particularly, to various methods offorming gate structures for semiconductor devices, such as transistorsand the like, using a replacement gate technique and the resultingsemiconductor devices.

2. Description of the Related Art

In modern integrated circuits, such as microprocessors, storage devicesand the like, a very large number of circuit elements, especiallytransistors, are provided and operated on a restricted chip area.Immense progress has been made over recent decades with respect toincreased performance and reduced feature sizes of circuit elements,such as transistors. However, the ongoing demand for enhancedfunctionality of electronic devices forces semiconductor manufacturersto steadily reduce the dimensions of the circuit elements and toincrease the operating speed of the circuit elements. The continuingscaling of feature sizes, however, involves great efforts in redesigningprocess techniques and developing new process strategies and tools so asto comply with new design rules. Generally, in complex circuitryincluding complex logic portions, MOS technology is presently apreferred manufacturing technique in view of device performance and/orpower consumption and/or cost efficiency. In integrated circuitsincluding logic portions fabricated by MOS technology, field effecttransistors (FETs) are provided that are typically operated in aswitched mode, that is, these devices exhibit a highly conductive state(on-state) and a high impedance state (off-state). The state of thefield effect transistor is controlled by a gate electrode, whichcontrols, upon application of an appropriate control voltage, theconductivity of a channel region formed between a drain region and asource region.

To improve the operating speed of FETs, and to increase the density ofFETs on an integrated circuit device, device designers have greatlyreduced the physical size of FETs over the years. More specifically, thechannel length of FETs has been significantly decreased, which hasresulted in improving the switching speed of FETs. However, decreasingthe channel length of a FET also decreases the distance between thesource region and the drain region. In some cases, this decrease in theseparation between the source and the drain makes it difficult toefficiently inhibit the electrical potential of the source region andthe channel from being adversely affected by the electrical potential ofthe drain. This is sometimes referred to as a so-called short channeleffect, wherein the characteristic of the FET as an active switch isdegraded.

In contrast to a FET, which has a planar structure, a so-called FinFETdevice has a three-dimensional (3D) structure. FIG. 1A is a perspectiveview of an illustrative prior art FinFET semiconductor device “A” thatis formed above a semiconductor substrate B that will be referenced soas to explain, at a very high level, some basic features of a FinFETdevice. In this example, the FinFET device A includes three illustrativefins C, a gate structure D, sidewall spacers E and a gate cap layer F.The gate structure D is typically comprised of a layer of gateinsulating material (not separately shown), e.g., a layer of high-kinsulating material (k-value of 10 or greater) or silicon dioxide, andone or more conductive material layers (e.g., metal and/or polysilicon)that serve as the gate electrode for the device A. The fins C have athree-dimensional configuration: a height H, a width W and an axiallength L. The axial length L corresponds to the direction of currenttravel in the device A when it is operational. The portions of the finsC covered by the gate structure D are the channel regions of the FinFETdevice A. In a conventional process flow, the portions of the fins Cthat are positioned outside of the spacers E, i.e., in the source/drainregions of the device A, may be increased in size or even mergedtogether (a situation not shown in FIG. 1A) by performing one or moreepitaxial growth processes. The process of increasing the size of ormerging the fins C in the source/drain regions of the device A isperformed to reduce the resistance of source/drain regions and/or makeit easier to establish electrical contact to the source/drain regions.Even if an epi “merger” process is not performed, an epi growth processwill typically be performed on the fins C to increase their physicalsize.

In the FinFET device, the gate structure D may enclose both the sidesand the upper surface of all or a portion of the fins C to form atri-gate structure so as to use a channel having a three-dimensionalstructure instead of a planar structure. In some cases, an insulatingcap layer (not shown), e.g., silicon nitride, is positioned at the topof the fins C and the FinFET device only has a dual-gate structure(sidewalls only). Unlike a planar FET, in a FinFET device, a channel isformed perpendicular to a surface of the semiconducting substrate so asto reduce the physical size of the semiconductor device. Also, in aFinFET, the junction capacitance at the drain region of the device isgreatly reduced, which tends to significantly reduce short channeleffects. When an appropriate voltage is applied to the gate electrode ofa FinFET device, the surfaces (and the inner portion near the surface)of the fins C, i.e., the vertically oriented sidewalls and the top uppersurface of the fin, form a surface inversion layer or a volume inversionlayer that contributes to current conduction. In a FinFET device, the“channel-width” is estimated to be about two times (2×) the verticalfin-height plus the width of the top surface of the fin, i.e., the finwidth. Multiple fins can be formed in the same foot-print as that of aplanar transistor device. Accordingly, for a given plot space (orfoot-print), FinFETs tend to be able to generate significantly higherdrive current density than planar transistor devices. Additionally, theleakage current of FinFET devices after the device is turned “OFF” issignificantly reduced as compared to the leakage current of planar FETs,due to the superior gate electrostatic control of the “fin” channel onFinFET devices. In short, the 3D structure of a FinFET device is asuperior MOSFET structure as compared to that of a planar FET,especially in the 20-nm CMOS technology node and beyond. The gatestructures D for such FinFET devices may be manufactured using so-called“gate-first” or “replacement gate” (gate-last) manufacturing techniques.

For many early device technology generations, the gate structures ofmost transistor elements (planar and FinFET devices) were comprised of aplurality of silicon-based materials, such as a silicon dioxide and/orsilicon oxynitride gate insulation layer, in combination with apolysilicon gate electrode. However, as the channel length ofaggressively scaled transistor elements has become increasingly smaller,many newer generation devices employ gate structures that containalternative materials in an effort to avoid the short channel effectswhich may be associated with the use of traditional silicon-basedmaterials in reduced channel length transistors. For example, in someaggressively scaled transistor elements, which may have channel lengthson the order of approximately 10-32 nm or less, gate structures thatinclude a so-called high-k dielectric gate insulation layer and one ormore metal layers that function as the gate electrode (HK/MG) have beenimplemented. Such alternative gate structures have been shown to providesignificantly enhanced operational characteristics over the heretoforemore traditional silicon dioxide/polysilicon gate structureconfigurations.

Depending on the specific overall device requirements, several differenthigh-k materials—i.e., materials having a dielectric constant, ork-value, of approximately 10 or greater—have been used with varyingdegrees of success for the gate insulation layer in an HK/MG gatestructure. For example, in some transistor element designs, a high-kgate insulation layer may include tantalum oxide (Ta₂O₅), hafnium oxide(HfO₂), zirconium oxide (ZrO₂), titanium oxide (TiO₂), aluminum oxide(Al₂O₃), hafnium silicates (HfSiO_(x)) and the like. Furthermore, one ormore non-polysilicon metal gate electrode materials—i.e., a metal gatestack—may be used in HK/MG configurations so as to control the workfunction of the transistor. These metal gate electrode materials mayinclude, for example, one or more layers of titanium (Ti), titaniumnitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon(TiALC), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalumnitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN),tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.

One well-known processing method that has been used for forming atransistor with a high-k/metal gate structure is the so-called “gatelast” or “replacement gate” technique. The replacement gate process maybe used when forming planar devices or 3D devices. FIGS. 1B-1Esimplistically depict one illustrative prior art method for forming anHK/MG replacement gate structure using a replacement gate technique on aplanar transistor device. As shown in FIG. 1B, the process includes theformation of a basic transistor structure above a semiconductingsubstrate 12 in an active area defined by a shallow trench isolationstructure 13. At the point of fabrication depicted in FIG. 1A, thedevice 10 includes a sacrificial gate insulation layer 14, a dummy orsacrificial gate electrode 15, sidewall spacers 16, a layer ofinsulating material 17 and source/drain regions 18 formed in thesubstrate 12. The various components and structures of the device 10 maybe formed using a variety of different materials and by performing avariety of known techniques.

For example, the sacrificial gate insulation layer 14 may be comprisedof silicon dioxide, the sacrificial gate electrode 15 may be comprisedof polysilicon, the sidewall spacers 16 may be comprised of siliconnitride and the layer of insulating material 17 may be comprised ofsilicon dioxide. The source/drain regions 18 may be comprised ofimplanted dopant materials (N-type dopants for NMOS devices and P-typedopants for PMOS devices) that are implanted into the substrate 12 usingknown masking and ion implantation techniques. Of course, those skilledin the art will recognize that there are other features of thetransistor 10 that are not depicted in the drawings for purposes ofclarity. For example, so-called halo implant regions are not depicted inthe drawings, as well as various layers or regions of silicon/germaniumthat are typically found in high performance PMOS transistors. At thepoint of fabrication depicted in FIG. 1B, the various structures of thedevice 10 have been formed and a chemical mechanical polishing (CMP)process has been performed to remove any materials above the sacrificialgate electrode 15 (such as a protective cap layer (not shown) comprisedof silicon nitride) so that at least the sacrificial gate electrode 15may be removed.

As shown in FIG. 1C, one or more etching processes are performed toremove the sacrificial gate electrode 15 and the sacrificial gateinsulation layer 14 to thereby define a replacement gate cavity 20 wherea replacement gate structure will subsequently be formed. Typically, thesacrificial gate insulation layer 14 is removed as part of thereplacement gate technique, as depicted herein. However, the sacrificialgate insulation layer 14 may not be removed in all applications. Even incases where the sacrificial gate insulation layer 14 is intentionallyremoved, there will typically be a very thin native oxide layer (notshown) that forms on the substrate 12 within the gate cavity 20.

Next, as shown in FIG. 1D, various layers of material that willconstitute a replacement gate structure 30 are formed in the gate cavity20. The materials used for the replacement gate structures 30 for NMOSand PMOS devices are typically different. For example, the replacementgate structure 30 for an NMOS device may be comprised of a high-k gateinsulation layer 30A, such as hafnium oxide, having a thickness ofapproximately 2 nm, a first metal layer 30B (e.g., a layer of titaniumnitride with a thickness of about 1-2 nm), a second metal layer 30C—aso-called work function adjusting metal layer for the NMOS device—(e.g.,a layer of titanium-aluminum or titanium-aluminum-carbon with athickness of about 5 nm), a third metal layer 30D (e.g., a layer oftitanium nitride with a thickness of about 1-2 nm) and a bulk metallayer 30E, such as aluminum or tungsten.

Ultimately, as shown in FIG. 1E, one or more CMP processes are performedto remove excess portions of the gate insulation layer 30A, the firstmetal layer 30B, the second metal layer 30C, the third metal layer 30Dand the bulk metal layer 30E positioned outside of the gate cavity 20 tothereby define the replacement gate structure 30 for an illustrativeNMOS device. Typically, the replacement gate structure 30 for a PMOSdevice does not include as many metal layers as does an NMOS device. Forexample, the gate structure 30 for a PMOS device may only include thehigh-k gate insulation layer 30A, a single layer of titanium nitride—thework function adjusting metal for the PMOS device—having a thickness ofabout 3-4 nm, and the bulk metal layer 30E.

FIG. 1F depicts the device 10 after several process operations wereperformed. First, one or more etching processes were performed to removeupper portions of the various materials within the cavity 20 so as toform a recess within the gate cavity 20. Then, a gate cap layer 31 wasformed in the recess above the recessed gate materials. The gate caplayer 31 is typically comprised of silicon nitride and it may be formedby depositing a layer of gate cap material so as to over-fill the recessformed in the gate cavity and, thereafter, performing a CMP process toremove excess portions of the gate cap material layer positioned abovethe surface of the layer of insulating material 17. The gate cap layer31 is formed so as to protect the underlying gate materials duringsubsequent processing operations.

As the gate length of transistor devices has decreased, the physicalsize of the gate cavity 20 has also decreased. Thus, it is becomingphysically difficult to fit all of the layers of material needed for thereplacement gate structure 30 within such reduced-size gate cavities,particularly for NMOS devices, due to the greater number of layers ofmaterial that are typically used to form the gate structures for theNMOS devices. For example, as gate lengths continue to decrease, voidsor seams may be formed as the various layers of material are depositedinto the gate cavity 20. FIG. 1G is a somewhat enlarged view of anillustrative NMOS device that is provided in an attempt to provide thereader with some idea of just how limited the lateral space 20S iswithin the gate cavity 20 of an NMOS device as the various metal layers30A-30D are formed in the gate cavity 20. In FIG. 1G, the internalsidewall surfaces of the spacers 16 define a gate cavity 20 having asubstantially uniform width 20S throughout the height or depth of thegate cavity 20. As the layers of material in the gate stack for thedevice are formed in the cavity 20, the remaining space 39 within thegate cavity 20 becomes very small. As the latter metal layers areformed, the lateral space 39 may be about 1-2 nm in width or evensmaller. In some cases, the space 39 may be essentially non-existent.This may lead to so-called “pinch-off” of metal layers such that voidsor seams may be formed in the overall gate stack, which may result indevices that perform at levels less than anticipated or, in some cases,the formation of devices that are simply not acceptable and have to bediscarded.

When manufacturing advanced integrated circuit products usingreplacement gate structures, particularly in situations where theproducts also include very tight spacing between source/drain contactstructures, such as products using self-aligned source/drain contacts,some amount of the work function metals in the gate cavity 20 must beremoved from the gate cavity 20 to make room for additional materials,i.e., to make room within the upper portion of the gate cavity 20 for abulk conductor material, such as tungsten and aluminum, and a gate caplayer. This process operation is sometimes referred to as work-functionchamfering. In such a work-function chamfering process, some form of aprotective material must be formed in the gate cavity 20 above the metallayer 30D to protect desired portions of the underlying metal layersduring the recess etching process. If the lateral space 39 (to theextent it exists) cannot be reliably filled with such a protectivematerial, such as a flowable oxide material, then the recessing etchingprocess cannot be performed for fear of removing desired portions of themetal layers during the course of performing the recess etching process.Additionally, due to the void/seam formation, the recessing process mayresult in a significant amount of non-uniformity in the recess etchingprocess and the resulting devices. Also, for devices with different gatelengths, e.g., 15 nm vs. 25 nm, the depth of the recessed gate may alsovary due to etch-loading effects, which increase the difficulty inperforming a uniform recess etching process.

The present disclosure is directed to various methods of forming gatestructures for semiconductor devices, such as transistors, using areplacement gate technique and the resulting semiconductor devices thatmay avoid, or at least reduce, the effects of one or more of theproblems identified above.

SUMMARY OF THE DISCLOSURE

The following presents a simplified summary of the disclosure in orderto provide a basic understanding of some aspects of the subject matterthat is described in further detail below. This summary is not anexhaustive overview of the disclosure, nor is it intended to identifykey or critical elements of the subject matter disclosed here. Its solepurpose is to present some concepts in a simplified form as a prelude tothe more detailed description that is discussed later.

Generally, the present disclosure is directed to various methods offorming gate structures for semiconductor devices, such as transistorsand the like, using a replacement gate technique and the resultingsemiconductor devices. One exemplary transistor device disclosed hereinincludes a semiconductor substrate and a gate structure positioned abovea surface of the semiconductor substrate. The gate structure includes,among other things, a high-k gate insulation layer positioned above thesurface of the semiconductor substrate and at least one work-functionadjusting layer of material positioned above the high-k gate insulationlayer, wherein an upper surface of the at least one work-functionadjusting layer of material has a stepped profile when viewed incross-section taken in a gate-width direction of the transistor device.Furthermore, the gate structure of the illustrative transistor devicealso includes a layer of conductive material positioned on the steppedupper surface of the at least one work-function adjusting layer ofmaterial.

Another illustrative transistor device of the presently disclosedsubject matter includes, among other things, a semiconductor substrate,a gate structure positioned above a surface of the semiconductorsubstrate, a gate cap layer positioned above a layer of conductivematerial, and a sidewall spacer positioned adjacent opposite sides ofeach of the gate structure and the gate cap layer. The gate structureincludes a high-k gate insulation layer positioned above the surface ofthe semiconductor substrate and at least one work-function adjustinglayer of material positioned above the high-k gate insulation layer. Theupper surface of the at least one work-function adjusting layer ofmaterial has a stepped profile when viewed in cross-section taken in agate-width direction of the transistor device, and the stepped profileincludes a plurality of substantially planar surfaces that are spacedapart from one another in the gate-width direction, wherein the uppersurface of each of the plurality of substantially planar spaced-apartsurfaces is positioned at approximately a same height level above thesurface of said semiconductor substrate. Additionally, the gatestructure of the exemplary transistor devices includes a layer ofconductive material positioned on the stepped upper surface of the atleast one work-function adjusting layer of material.

In a further exemplary embodiment of the present disclosure, anillustrative transistor device includes a semiconductor substrate, agate structure positioned above a surface of the semiconductorsubstrate, and a sidewall spacer positioned adjacent opposite sides ofat least a portion of the gate structure. The gate structure includes,among other things, a gate insulation layer positioned above the surfaceof the semiconductor substrate, a layer of gate electrode materialpositioned above the gate insulation layer, the upper surface of thelayer of gate electrode material having a stepped profile when viewed incross-section taken in a gate-width direction of the transistor device,and a layer of conductive material positioned on the stepped uppersurface of the layer of gate electrode material. The stepped profile ofthe upper surface of the layer of gate electrode material includes aplurality of periodically spaced-apart upper surface portions, each ofwhich has a substantially planar upper surface that is positioned atapproximately a same first height level above the upper surface of thesemiconductor substrate. Additionally, the stepped profile of the uppersurface of the layer of gate electrode material further includes aprojection positioned between a first two of the plurality ofspaced-apart upper surface portions and a recess positioned between asecond two of the plurality of spaced-apart upper surface portions,wherein the upper surface of the projection is positioned at a secondheight level above the upper surface of the semiconductor substrate thatis greater than the first height level, and the upper surface of therecess is positioned at a third height level above the upper surface ofthe semiconductor substrate that is less than the first height level.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIG. 1A is a perspective view of one illustrative embodiment of a priorart FinFET device;

FIGS. 1B-1G depict one illustrative prior art method of forming a gatestructure of a transistor using a so-called “replacement gate”technique; and

FIGS. 2A-2K depict various illustrative methods disclosed herein offorming gate structures for semiconductor devices using a replacementgate technique and the resulting semiconductor devices.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention.

DETAILED DESCRIPTION

Various illustrative embodiments of the present subject matter aredescribed below. In the interest of clarity, not all features of anactual implementation are described in this specification. It will ofcourse be appreciated that in the development of any such actualembodiment, numerous implementation-specific decisions must be made toachieve the developers' specific goals, such as compliance withsystem-related and business-related constraints, which will vary fromone implementation to another. Moreover, it will be appreciated thatsuch a development effort might be complex and time-consuming, but wouldnevertheless be a routine undertaking for those of ordinary skill in theart having the benefit of this disclosure.

The present subject matter will now be described with reference to theattached figures. Various systems, structures and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

The present disclosure generally relates to various methods of forminggate structures for semiconductor devices using a replacement gatetechnique. Moreover, as will be readily apparent to those skilled in theart upon a complete reading of the present application, the presentmethod is applicable to a variety of devices, including, but not limitedto, logic devices, memory devices, etc., and the methods disclosedherein may be employed to form N-type or P-type semiconductor devices.The methods and devices disclosed herein may be employed inmanufacturing products using a variety of technologies, NMOS, PMOS,CMOS, etc., and they may be employed in manufacturing a variety ofdifferent devices, e.g., memory devices, logic devices, ASICs, etc. Ofcourse, the inventions disclosed herein should not be considered to belimited to the illustrative examples depicted and described herein. Withreference to the attached figures, various illustrative embodiments ofthe methods and devices disclosed herein will now be described in moredetail.

As will be appreciated by those skilled in the art after a completereading of the present application, the methods and structures disclosedherein may be used when forming either planar or 3D transistor devices.An illustrative device 100 in the form of a planar device will bedepicted for purposes of disclosing the subject matter set forth herein.Additionally, various doped regions, e.g., source/drain regions, haloimplant regions, well regions and the like, are not depicted in theattached drawings. Of course, the inventions disclosed herein should notbe considered to be limited to the illustrative examples depicted anddescribed herein. Moreover, the transistor devices that are depicted inthe attached drawings may be either NMOS or PMOS devices. Theillustrative transistor device 100 depicted in the drawings is formedabove an illustrative substrate 102 that may have a variety ofconfigurations, such as the depicted bulk silicon configuration. Thesubstrate 102 may also have a silicon-on-insulator (SOI) configurationthat includes a bulk silicon layer, a buried insulation layer and anactive layer, wherein semiconductor devices are formed in and above theactive layer. Thus, the terms “substrate” or “semiconductor substrate”should be understood to cover all semiconducting materials and all formsof such materials.

In general, the drawings contain a plan view and various cross-sectionalviews that are taken where indicated in the plan view. As shown in theplan view in FIG. 2A, the views “X-X” and “Z-Z” are cross-sectionalviews taken through the gate structure of the device 100 in thegate-length direction of the device 100 at different locations along thegate structure. The view “Y-Y” is a cross-sectional view that is takenthrough the long axis of the gate structure, i.e., a cross-sectionalview through the gate structure in the gate-width direction of thetransistor device.

In the examples disclosed herein, the device 100 will be formed using areplacement gate technique. Accordingly, FIG. 2A depicts the device 100at a point in fabrication wherein several layers of material andstructures have been formed above the substrate 102. More specifically,at the point of fabrication depicted in FIG. 2A, the device 100 includesa sacrificial gate structure 104 comprised of a sacrificial gateinsulation layer 106, a lower dummy or sacrificial gate electrode 108,an upper sacrificial or dummy gate electrode 110, sidewall spacers 111and a layer of insulating material 112. Also depicted in FIG. 2A, view“Y-Y,” are schematically depicted isolation regions 114 that have beenformed in the substrate 102. FIG. 2A depicts the device 100 after one ormore chemical mechanical polishing (CMP) processes were performed toremove any materials above the sacrificial gate electrode 110 (such asthe protective cap layer (not shown)) such that the upper surface 110Sof the upper sacrificial gate electrode 110 is exposed.

The device depicted in FIG. 2A may be comprised of a variety ofdifferent materials, e.g., the sacrificial gate insulation layer 106 maybe comprised of silicon dioxide. In general, the lower sacrificial gateelectrode 108 and the upper sacrificial gate electrode 110 should bemade of materials that exhibit a high degree of etch selectivelyrelative to one another. Thus, in one embodiment, the lower sacrificialgate electrode 108 may be comprised of silicon-germanium(Si_(x)Ge_(1-x)) while the upper sacrificial gate electrode 110 may becomprised of a silicon-containing material such as silicon, polysiliconor amorphous silicon, etc. The sidewall spacers 111 and the gate caplayer (not shown) may be comprised of silicon nitride while the layer ofinsulating material 112 and the isolation regions 114 may be comprisedof silicon dioxide. The sidewall spacers 111 may be formed by depositinga layer of spacer material and thereafter performing an anisotropicetching process to produce the spacers 111. Also depicted in FIG. 2A areregions of illustrative epi semiconductor material 113 that were formedin/or above the source/drain regions of the device 100. Of course, suchepi semiconductor material 113 need not be formed to practice thevarious inventions disclosed herein. The various components andstructures of the device 100 disclosed herein may be formed using avariety of different materials and by performing a variety of knowntechniques, e.g., a chemical vapor deposition (CVD) process, an atomiclayer deposition (ALD) process, a thermal growth process, spin-coatingtechniques, etc. The thicknesses of these various layers of material mayalso vary depending upon the particular application.

FIG. 2B depicts the device 100 after a patterned masking layer 116,e.g., a patterned hard mask layer, has been formed above the substrate102. The patterned masking layer 116 has a plurality of openings 116Aspaced apart along the gate-width direction of the sacrificial gatestructure 104. That is, the patterned masking layer 116 exposes some,but not all, of the upper sacrificial gate electrode 110. The size ofthe openings 116A may vary depending upon the particular application.The openings 116A have a bar-shaped configuration to ensure that, evenif there is some horizontal misalignment, the desired portions of theupper sacrificial gate electrode 110 are exposed. In some embodiments,the size 116X of the openings 116A (in the gate width direction) may beon the order of about the gate length dimension (L_(g)) of the device100 or slightly larger than L_(g). Additionally, the density of theopenings 116A may be smaller than the density of the various gatestructures formed above the substrate 102. The view Z-Z is taken throughthe gate structure 104 and one of the openings 116A in the masking layer116. The view X-X is taken through the gate structure 104 at a pointoutside of the openings 116A. Note that the plan view in FIG. 2B (andsubsequent drawings) does not agree with the cross-sectional view Z-Z interms of the number of openings 116A depicted (two in the plan viewversus three in view Z-Z) so as not to overcrowd the plan view drawingand hopefully facilitate disclosures of various aspects disclosedherein.

The patterned masking layer 116 is intended to be representative innature as it may be comprised of a variety of materials, such as, forexample, a photoresist material, silicon nitride, silicon oxynitride,etc. Moreover, the patterned masking layer 116 may be comprised ofmultiple layers of material, such as, for example, a silicon nitridelayer and a layer of silicon dioxide. The patterned masking layer 116may be formed by depositing the layer(s) of material that comprise themasking layer 116 and thereafter directly patterning the masking layer116 using known photolithography and etching techniques. Alternatively,the patterned masking layer 116 may be formed by using known sidewallimage transfer techniques. Thus, the particular form and composition ofthe patterned masking layer 116 and the manner in which it is madeshould not be considered a limitation of the present invention. In thecase where the patterned masking layer 116 is comprised of one or morehard mask layers, such layers may be formed by performing a variety ofknown processing techniques, such as a chemical vapor deposition (CVD)process, an atomic layer deposition (ALD) process, an epitaxialdeposition process (EPI), or plasma enhanced versions of such processes,and the thickness of such a layer(s) may vary depending upon theparticular application.

FIG. 2C depicts the device 100 after an anisotropic etching process wasperformed through the patterned masking layer 116 to remove the exposedportions of the upper sacrificial gate electrode 110 selectivelyrelative to the lower sacrificial gate electrode 108 and the interlayerdielectric 112. This etching process results in the definition of aplurality of trenches 110A that expose the upper surface 108S of thelower sacrificial gate electrode 108. The etching process also resultsin a patterned upper sacrificial gate electrode 110P. Note that, due tothe nature of the trench etching process, the sidewalls 110S of thetrenches 110A are inwardly tapered, thereby resulting in the trenches110A being wider at the top of the trench 110A than they are at thebottom of the trench 110A.

FIG. 2D depicts the device 100 after the patterned masking layer 116 wasremoved.

Next, as shown in FIG. 2E, one or more wet isotropic etching processeswere performed through the trenches 110A in the patterned uppersacrificial gate electrode 110P to remove the lower sacrificial gateelectrode 108 selectively relative to the upper sacrificial gateelectrode 110 and the surrounding materials and to remove thesacrificial gate insulation layer 106. This etching process results inthe definition of a space or cavity 120 under the patterned uppersacrificial gate electrode 110P and also exposes the upper surface 102Sof the substrate 102. The cavity or space 120 effectively defines afirst portion of what will ultimately become the replacement gate cavity118 for the final replacement gate structure for the device 100.

The next major process sequence involves formation of portions of thereplacement gate structure for the device 100. The replacement gatestructure that will be depicted herein is intended to be representativein nature of any type of gate structure that may be employed inmanufacturing integrated circuit products using so-called gate-last(replacement-gate) manufacturing techniques. Accordingly, with referenceto FIG. 2F, a pre-clean process was performed in an attempt to removeall foreign materials from within the replacement gate cavity 118, i.e.,within the cavity 120 and the openings 110A in the patterned uppersacrificial gate electrode 110P, prior to forming the various layers ofmaterial that will become part of the replacement gate structure. Next,a high-k (k value greater than 10) gate insulation layer 121, such ashafnium oxide (or the other high-k materials noted in the backgroundsection of this application), was deposited across the device 100 andwithin the first portion of the replacement gate cavity 118 above thesubstrate 102 by performing a conformal deposition process, i.e., an ALDor CVD deposition process. If desired, a thin interfacial layer ofsilicon dioxide (not shown) may be formed prior to the formation thehigh-k gate insulation layer 121. That is, the high-k gate insulationlayer 121 is formed on the surface 102S of the substrate and on thebottom surfaces 110B and sidewalls 1105 of the patterned uppersacrificial gate electrode 110P. Next, at least one work functionadjusting metal layer 122 (e.g., a layer of titanium nitride or TiAlCdepending upon the type of transistor device being manufactured) wasdeposited on the high-k gate insulation layer 121 and within the firstportion of the replacement gate cavity 118 by performing a conformal ALDor CVD deposition process. Of course, the work function adjusting metallayer 122 may be comprised of any of the metals described in thebackground section of this application and more than one layer of workfunction metal may be formed in the replacement gate cavity 118,depending upon the particular device under construction. Due to the verysmall sizes of the replacement gate cavities 118 in modern transistordevices, even using the novel methods disclosed herein, the formation ofthe work function adjusting metal layer 122 may result in the formationof very narrow openings or voids 124, i.e., pinch-off may occur.

FIG. 2G depicts the device 100 after one or more timed, wet or dryetching processes were performed to remove the desired amounts of thework function adjusting metal layer 122 and the high-k gate insulationlayer 121 so as to make room within the upper portion of the gate cavity118 for a bulk conductor material, such as tungsten and aluminum, and agate cap layer. These process operations expose uneven surfaces 122A-Cof the work function adjusting metal layer 122. The degree of unevennessof the surfaces 122A-C is exaggerated in the drawings for purposes ofexplanation. However, as compared to the prior art technique of formingreplacement gate structures, the unevenness of the surfaces 122A-C isless and, moreover, it is more uniform across all of the devices thatare formed above the substrate, i.e., there is less device-to-devicevariations. This is due, in part, to the fact that the size of theopening of the trenches 110A in the patterned upper sacrificial gateelectrode 110P is substantially uniform across all of the variousdevices being formed and because the inwardly tapered shape of thetrenches 110A can be readily controlled. Thus, even if the work functionmetal 122 exhibits some surface non-uniformity, the total density ofsuch nonuniformities is along the gate-width direction of the device 100since the bottom surface 110B of the remaining portions of the patternedupper sacrificial gate electrode 110P insure that substantial portionsof the work function adjusting metal layer 122 and high-k gateinsulation layer 121, i.e., the portions underlying the patterned uppersacrificial gate electrode 110P, are substantially planar.

FIG. 2H depicts the device 100 after one or more etching processes wereperformed to remove the patterned upper sacrificial gate electrode 110Pselectively relative to the work function adjusting metal layer 122, thehigh-k gate insulation layer 121 and the surrounding structures. Removalof the patterned upper sacrificial gate electrode 110P defines theremaining portion of the replacement gate cavity 118.

FIG. 2I depicts the device 100 after one or more etching processes wereperformed to remove the substantially horizontally oriented portions ofthe high-k gate insulation layer 121 selectively relative to the workfunction adjusting metal layer 122 and the surrounding structures. Thisexposes the spaced-apart, substantially planar, upper surfaces 123A-D ofthe work function adjusting metal layer 122 that were positioned underthe remaining portions of the patterned upper sacrificial gate electrode110P and therefore not subjected to the recess etching process depictedin FIG. 2G. The substantially planar surfaces 123A-D are laterallyspaced apart from one another along the gate-width direction 101 of thedevice 100. As depicted, using the methods disclosed herein, the overallupper surface 122X of the work function metal 122 has an up/down steppedconfiguration when viewed in cross-section along the gate-widthdirection 101, i.e., in the view Y-Y. Moreover, the up/down steps inthis stepped configuration are periodic, not random. For example, in thegate width direction 101, the projection represented by the surface 122Bis positioned between the substantially planar surfaces 123B and 123C.Also note that the substantially planar surfaces 123A-D each has anupper surface that is positioned at approximately the same height levelabove the surface 102S of the substrate 102. It is also worth notingthat the projections represented by the surfaces 122A and 122B arepositioned at a height level that is above the upper surfaces of thespaced-apart, substantially planar surfaces 123A-D relative to the uppersurface 102S of the substrate 102. Furthermore, the upper surface of therecessed surface 122C is positioned at a height level that is below anupper surface of the spaced-apart, substantially planar surfaces 123A-Drelative to the upper surface 102S of the substrate 102.

FIG. 2J depicts the device 100 after several process operations wereperformed. First, a bulk conductive material layer 125, such as tungstenor aluminum, was blanket-deposited above the substrate so as toover-fill the replacement gate cavity 118 and deposit the bulkconductive material layer 125 on the overall stepped upper surface 122Xof the work function adjusting metal layer 122. Thereafter, a CMPprocess was performed to remove excess portions of the bulk conductivematerial layer 125 positioned above the surface of the layer ofinsulating material 112. Next, a recess etching process was performed soas to remove a desired amount of the bulk conductive material layer 125and thereby define a gate cap cavity 126 above the recessed bulkconductive material layer 125. The combination of the high-k gateinsulation layer 121, the work function adjusting metal layer 122 andthe recessed bulk conductive material layer 125 shown in FIG. 2Jconstitutes the final replacement gate structure 130 for the device 100.

FIG. 2K depicts the device 100 after an illustrative gate cap layer 127was formed in the recess 126 above the recessed bulk conductive materiallayer 125. The gate cap layer 127 may be formed from a variety ofdifferent materials, e.g., typically silicon nitride. The gate cap layer127 may be formed by depositing a layer of gate cap material so as toover-fill the recess 126 formed in the replacement gate cavity 118 abovethe replacement gate structure 130 and, thereafter, performing a CMPprocess to remove excess portions of the gate cap material layerpositioned above the surface of the layer of insulating material 112.The gate cap layer 127 is formed so as to protect the underlying gatematerials during subsequent processing operations.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Note that the use of terms, such as “first,” “second,”“third” or “fourth” to describe various processes or structures in thisspecification and in the attached claims is only used as a shorthandreference to such steps/structures and does not necessarily imply thatsuch steps/structures are performed/formed in that ordered sequence. Ofcourse, depending upon the exact claim language, an ordered sequence ofsuch processes may or may not be required. Accordingly, the protectionsought herein is as set forth in the claims below.

What is claimed:
 1. A transistor device, comprising: a semiconductorsubstrate; and a gate structure positioned above a surface of saidsemiconductor substrate, said gate structure comprising: a high-k gateinsulation layer positioned above said surface of said semiconductorsubstrate; at least one work-function adjusting layer of materialpositioned above said high-k gate insulation layer, wherein an uppersurface of said at least one work-function adjusting layer of materialhas a stepped profile when viewed in cross-section taken in a gate-widthdirection of said transistor device; and a layer of conductive materialpositioned on said stepped upper surface of said at least onework-function adjusting layer of material.
 2. The device of claim 1,wherein said stepped profile of said upper surface of said at least onework-function adjusting layer of material comprises a plurality ofsubstantially planar surfaces that are spaced apart from one another insaid gate-width direction.
 3. The device of claim 2, wherein an uppersurface of each of said plurality of substantially planar spaced-apartsurfaces is positioned at approximately a same height level above saidsurface of said semiconductor substrate.
 4. The device of claim 2,wherein said stepped profile of said upper surface of said at least onework-function adjusting layer of material further comprises at least oneprojection positioned between said plurality of spaced-apart,substantially planar surfaces, an upper surface of said at least oneprojection being positioned at a height level above said upper surfaceof said semiconductor substrate that is greater than a height level ofan upper surface of said spaced-apart, substantially planar surfacesabove said upper surface of said semiconductor substrate.
 5. The deviceof claim 4, wherein said at least one projection comprises an openingextending below said upper surface of said at least one projection. 6.The device of claim 5, wherein said layer of conductive material fillssaid opening extending below said upper surface of said at least oneprojection.
 7. The device of claim 2, wherein said stepped profile ofsaid upper surface of said at least one work-function adjusting layer ofmaterial further comprises at least one recess positioned between saidplurality of spaced-apart, substantially planar surfaces, an uppersurface of said at least one recess being positioned at a height levelabove said upper surface of said semiconductor substrate that is lessthan a height level of an upper surface of said spaced-apart,substantially planar surfaces above said upper surface of saidsemiconductor substrate.
 8. The device of claim 1, wherein said steppedprofile of said upper surface of said at least one work-functionadjusting layer of material comprises a plurality of periodicallyspaced-apart upper surface portions, each of said plurality ofperiodically spaced-apart upper surface portions having a substantiallyplanar upper surface that is positioned at approximately a same heightlevel above said upper surface of said semiconductor substrate.
 9. Thedevice of claim 1, further comprising a sidewall spacer positionedadjacent opposite sides of said gate structure.
 10. The device of claim9, further comprising a gate cap layer positioned above said layer ofconductive material.
 11. The device of claim 10, wherein said sidewallspacer is positioned adjacent opposite sides of said gate cap layer. 12.A transistor device, comprising: a semiconductor substrate; a gatestructure positioned above a surface of said semiconductor substrate,said gate structure comprising: a high-k gate insulation layerpositioned above said surface of said semiconductor substrate; at leastone work-function adjusting layer of material positioned above saidhigh-k gate insulation layer, wherein an upper surface of said at leastone work-function adjusting layer of material has a stepped profile whenviewed in cross-section taken in a gate-width direction of saidtransistor device, said stepped profile comprising a plurality ofsubstantially planar surfaces that are spaced apart from one another insaid gate-width direction, wherein an upper surface of each of saidplurality of substantially planar spaced-apart surfaces is positioned atapproximately a same height level above said surface of saidsemiconductor substrate; and a layer of conductive material positionedon said stepped upper surface of said at least one work-functionadjusting layer of material; a gate cap layer positioned above saidlayer of conductive material; and a sidewall spacer positioned adjacentopposite sides of each of said gate structure and said gate cap layer.13. The device of claim 12, wherein said stepped profile of said uppersurface of said at least one work-function adjusting layer of materialfurther comprises at least one projection positioned between saidplurality of spaced-apart, substantially planar surfaces, an uppersurface of said at least one projection being positioned at a heightlevel above said upper surface of said semiconductor substrate that isgreater than a height level of an upper surface of said spaced-apart,substantially planar surfaces above said upper surface of saidsemiconductor substrate.
 14. The device of claim 12, wherein saidstepped profile of said upper surface of said at least one work-functionadjusting layer of material further comprises at least one recesspositioned between said plurality of spaced-apart, substantially planarsurfaces, an upper surface of said at least one recess being positionedat a height level above said upper surface of said semiconductorsubstrate that is less than a height level of an upper surface of saidspaced-apart, substantially planar surfaces above said upper surface ofsaid semiconductor substrate.
 15. The device of claim 12, wherein saidstepped profile of said upper surface of said at least one work-functionadjusting layer of material comprises a plurality of periodicallyspaced-apart upper surface portions, each of said plurality ofperiodically spaced-apart upper surface portions having a substantiallyplanar upper surface that is positioned at approximately a same heightlevel above said upper surface of said semiconductor substrate.
 16. Atransistor device, comprising: a semiconductor substrate; a gatestructure positioned above a surface of said semiconductor substrate,said gate structure comprising: a gate insulation layer positioned abovesaid surface of said semiconductor substrate; a layer of gate electrodematerial positioned above said gate insulation layer, wherein an uppersurface of said layer of gate electrode material has a stepped profilewhen viewed in cross-section taken in a gate-width direction of saidtransistor device, said stepped profile comprising: a plurality ofperiodically spaced-apart upper surface portions, each of said pluralityof periodically spaced-apart upper surface portions having asubstantially planar upper surface that is positioned at approximately asame first height level above said upper surface of said semiconductorsubstrate; a projection positioned between a first two of said pluralityof spaced-apart upper surface portions, wherein an upper surface of saidprojection is positioned at a second height level above said uppersurface of said semiconductor substrate that is greater than said firstheight level; and a recess positioned between a second two of saidplurality of spaced-apart upper surface portions, wherein an uppersurface of said recess is positioned at a third height level above saidupper surface of said semiconductor substrate that is less than saidfirst height level; and a layer of conductive material positioned onsaid stepped upper surface of said layer of gate electrode material; anda sidewall spacer positioned adjacent opposite sides of at least aportion of said gate structure.
 17. The device of claim 16, furthercomprising a gate cap layer positioned above said layer of conductivematerial, wherein said sidewall spacer is positioned adjacent oppositesides of at least a portion of said gate gap layer.
 18. The device ofclaim 16, wherein said gate insulation layer comprises a high-kdielectric material having a dielectric constant of approximately 10 orgreater.
 19. The device of claim 16, wherein said layer of gateelectrode material comprises at least one work-function adjusting metallayer.
 20. The device of claim 16, wherein said gate structure is anHK/MG replacement gate structure.